A FinFET is a transistor architecture of the metal-oxide-semiconductor field-effect transistor (MOSFET) type, which is favored as a replacement for planar MOSFET transistors in future integrated circuits fabricated in MOS technology, such as NMOS, PMOS, CMOS or BiCMOS.
A FinFET comprises a gate structure, which is wrapped around three sides of a fin-shaped channel region that stands vertically on a substrate surface. The substrate surface is assumed as being oriented horizontally for the purpose of this description. In contrast to planar MOSFET transistors, which have a channel region in parallel orientation to the substrate surface, FinFETs allow superior channel charge control even at extremely short gate lengths.
Although FinFETs are considered double-gate MOSFET structures, the two gates of a FinFET are often physically and electrically connected. In contrast, U.S. Pat. No. 6,611,029 B1 discloses a FinFET that has separate gates. The gates are arranged on opposite lateral sides of the fin. A top fin face is covered by a dielectric layer that electrically insulates the two gates from each other.
FinFETs with separate gates share the additional advantages of planar MOSFETs with two independent gates. The gates can be addressed individually. For instance, a channel or gate biasing can be applied by controlling the voltage applied to one of the two gates in order to vary the transistor threshold voltage. The other gate, which is not used for threshold voltage adjustment, is used to switch the transistor and to drive current through the channel.
The fabrication of a FinFET with separate gates is not trivial. In U.S. Pat. No. 6,611,029 B1, the processing involves the use of a protective dielectric cap during an etching process for the formation of the fin on an originally buried oxide layer of the substrate. Subsequently, source and drain regions are formed adjacent to longitudinal ends of the fin. Then, a dielectric layer is thermally grown on the lateral faces of the fin. The dielectric layer forms the gate isolation layer. Subsequently, a gate material layer is deposited over the fin and then patterned by lithography, followed by planarizing the gate material in a chemical-mechanical polishing (CMP) treatment. The CMP treatment is performed such that the gate material is even with the dielectric cap in the vertical direction. This separates the gate material into two separate gate layers. The dielectric cap assumes the function of a gate separation layer in this step. The processing then continues with the formation of gate electrodes and other known steps.
Considering the small dimensions of the fin in current and future MOS technology nodes, this processing is not only very tedious but also very sensitive to process variations and misalignment. Furthermore, the integration of the FinFET processing of U.S. Pat. No. 6,611,029 B1 into conventional MOS processing schemes is very expensive.
In addition, the fabrication of a combination of a first type of FinFETs having two separated gates with a second type of FinFETs having a single continuous gate on a single wafer would be very costly on the basis of the method known from U.S. Pat. No. 6,611,029 B1. The CMP treatment that separates the gates into two gate layers affects the whole wafer and does not allow differentiating between the FinFETs of the first and second type. As a consequence, the FinFETs of the second type would either have to be fabricated separately after the FinFETs of the first type, or some kind of repair of the gate layer would have to be selectively performed on the FinFETs of the second type, which would require special efforts to avoid extensive defect formation in the gate stack and thus poor device performance.
Furthermore, the mentioned prior art does not address a situation, in which different gate-electrode materials are needed, e.g. for NMOS and PMOS transistors. The CMP process may be particularly sensitive to one, but not the other.
It would therefore be desirable to provide an alternative FinFET structure with separate gates and a method for fabricating a FinFET with separate gates, which remove or mitigate these disadvantages.